Efficient Compressor and Encoder Strategies for Cost-Effective Radix-4 Approximate Booth Multipliers

Multiplication operations are essential in digital systems, and the design of efficient and cost-effective multipliers holds significant importance across various applications. This paper presents a novel methodology aimed at improving the affordability of approximate radix-4 Booth multipliers by proposing simplified designs for compressors and encoders. The primary objective is to achieve a balance between computational accuracy and hardware cost, rendering the multiplier suitable for deployment in low-cost embedded systems and applications where a certain degree of approximation is permissible. The proposed approach involves utilization of simplified compressors, meticulously optimized for resource efficiency and seamless integration into the approximate radix-4 Booth multiplier architecture. Furthermore, an innovative encoder design is introduced to further streamline the hardware complexity associated with encoding partial products. These encoder designs are strategically crafted to maintain an acceptable level of accuracy while minimizing resource utilization.