PARAMETER ANALYSIS OF SRAM CIRCUIT
Deepti Sagar1, Er. Thakurendra Singh2
Electronic & Communication Engineering, RBS Engineering Technical Campus Agra1
Electronic & Communication Engineering, RBS Engineering Technical Campus Agra2
Abstract: The study examined the different a number of power-saving strategies, including sleep, stack, sleep stack, transmission gate logic, or self-controllable voltage level-upper (SVL-U). These methods are used with SRAM cells that have 6 transistors (6T), 7 transistors (8T), 8 transistors (9T), and 10 transistors (10T). The SVL-U method and transmission gate logic are used in suggested SRAM cell. According to a comparison of SRAM memory array as well as cells, dynamic power is significantly decreased on average when compared to traditional methods. The 45nm and 90nm software applications from Cadence are also used for simulation. According to a thorough analysis of SRAM memory arrays and cells, PDP and EDP have, on average, been significantly decreased when contrasted the state-of-the-art hybrid VLSI techniques. Therefore, these SRAMs are suitable for extremely low power embedded structural appliances.
Keywords: Semiconductor Memories, Memory organization, SRAM, Write operation, Read Operation.
