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Stream/Area:
-
Subject:
-
Paper ID:
10.55041/IJSREM39697
Volume:
8 |
12 |
Dec 2024
Pages:
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.
This paper presents the design details and imple- mentation of FPGA results of 64-bit ALU based on Vedas such as Urdhva Tiryakbhyam and Nikhilam. After performing the Veda calculation, the equation reached the result in 4.014 seconds. Xilinx Spartan FPGA products complete the ALU module written in Verilog HDL. Play After checking the balance process in detail, the Xilinx ISE 12.3 program is used to get the results. The results show that: More work can be done using Vedas. Application of Arithmetic 85
KEYWORDS
Publication Date
12/22/2024
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
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Conflict of Interest
The authors declare no conflict of interest related to this research work.
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