A 7T SECURITY ORIENTED SRAM BITCELL

A 7T SECURITY ORIENTED SRAM BITCELL

C.Durga Tejaswi, M.Nithesh kumar²,N.Vineeth², V.Srinivasulu Reddy²,V.Ananth Babu².

¹Assistant Professor, Department of ECE, Narayana Engineering College, Gudur, AP, 524101.

²UG Student, Department of ECE, Narayana Engineering College, Gudur, AP,524101.

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Abstract – Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented with six-transistor (6T) static random access memory (SRAM) cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel power analysis attacks due to the correlation between their current characteristics and written data. To provide resiliency to these types of attacks, we propose a security-oriented 7T SRAM cell, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations. The proposed 7T SRAM cell was implemented in a 28 nm technology and demonstrates over 1000× lower write energy standard deviation between write ‘1’ and ‘0’ operations compared to a conventional 6T SRAM. In addition, the proposed cell has a 39%–53% write energy reduction and a 19%–38% reduced write delay compared to other power analysis resistant SRAM cells.

Key Words: Power Analysis, SRAM Design, 6T SRAM, 7T SRAM, Power Dissipation

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