A Comprehensive Review on Signal-Conditioning Subsystems Using 90nm CMOS Technology

This paper reviews the signal-conditioning subsystems designed and implemented in 90nm CMOS technology, emphasizing the critical role of analog functional blocks in modern mixed-signal integrated systems. The review focuses on key components including operational amplifiers, buffers, sample-and hold circuits, comparators, and encoding interfaces, addressing primary design challenges: voltage headroom limitations, increased leakage currents, parasitic effects, and short-channel phenomena inherent to deep- submicron processes. Special attention is given to layout-aware design methodologies, pre-layout versus post-layout performance variations, and subsystem characterization using Cadence Virtuoso with gpdk090nm PDK. Performance metrics including gain, bandwidth, noise, linearity, speed, and power consumption are systematically evaluated across process-voltage temperature corners. The study emphasizes efficient design flow encompassing schematic simulation, comprehensive layout design with parasitic extraction, and post- layout verification to validate analog performance despite deep- submicron constraints. The comprehensive review will provide engineers and researchers with a unified reference for developing robust, power-efficient signal conditioning circuits suitable for sensor acquisition front-ends, low-power mixed-signal SoCs, and industrial sensing modules.