A DFT -Compatible Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead

As integrated circuits become more susceptible to process, voltage, and temperature variations, timing error resilience through EDAC structures is essential. However, conventional EDAC approaches often introduce design-for-testability (DFT) issues due to the presence of latch-based data paths and additional control logic. This paper proposes a DFT-compatible EDAC structure featuring a Scannable EDAC Cell (SEDC) that enables seamless integration of error detection in functional mode and efficient shift operations in scan mode. The architecture allows simplified control of detection logic and leverages global error propagation for straightforward observation. A shift-based testing methodology is further presented, minimizing test-pattern complexity and test time while preserving high fault coverage and low area overhead.