A Hierarchical Priority Based Multi-Bit Error Tolerant Design for FPGA Configuration Memory

A Hierarchical Priority Based Multi-Bit Error Tolerant Design for FPGA Configuration Memory

1st Pavana J, 2nd Lisa C

1 M.Tech Student,VLSI
2 Assistant Professor
Electronics and Communication Engineering
Nehru College of Engineering and Research Centre
Pampady,Thrissur,Kerala,India

Abstract—The reconfigurability of a field-programmable gate array (FPGA), which is utilized in many applications, permits changes to be made to an existing design. In hostile environments such as space, where radiation and ionizing particles increase the risk for failure and human maintenance is either impossible or time-consuming, this reconfigurable capability becomes even more important. Single event upsets (SEUs) and multi-bit upsets (MBUs) on configuration memory can cause soft errors and circuit malfunctions in SRAM-based field programmable gate arrays (FPGAs). The ever-increasing quantity of configuration bits in contemporary FPGAs makes it more difficult for traditional scrubbing to identify faults in a timely manner, leading to a mismatch between scrubbing performance and MBU sensitivity.A hierarchical multi-bit error correcting method fully utilizes the MBU sensitivity at various configuration frame locations. It employs distinct techniques for varying priorities and differentiates across configuration frames with multiple priorities. They divided code words into several sections and used distinct error-correction techniques in each section. In high radiation conditions, the suggested integrated error correction technique enhances FPGA configuration memory protection by substituting memory scrubbing. The suggested approach lowers total TTD and enables priority-based asynchronous MBU detection and correction.

Index Terms—FPGA,MBU,Sensitivity,Configuration memory