A Review: Implementation of 16x16 SRAM Memory Array Using 180nm Technology

SRAM is a crucial part of cache and is used in a wide range of products, such as microprocessors and data storage devices, which occupy a sizable portion of die area and consume a lot of energy. Memories should use less energy so that systems operate more reliably and efficiently. In order to reduce leakage power and maximise performance, we developed a 16×16 SRAM array. This was accomplished by, to a limited extent, relaxing the peripherals area concerns through the design of peripherals that take up less space and use less energy. Additional power usage can be reduced using the forced transistor method and the sleep transistor technique. The study finds that the sleep transistor method causes 99.94% more delay than the forced stack transistor technique, but the forced technique causes 56.92% less power consumption. The 16×16 SRAM memory was designed, built, and examined in a typical UMC 180nm technology using the Cadence tool.