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ArticlePeer ReviewedOpen AccessPlagiarism Passed
Paper ID:10.55041/IJSREM36877

A Review on FPGA-based Architectures for Noise Removal of Digital Images using High-Level Design

Stream/Area:

-

Subject:

-

Paper ID:

10.55041/IJSREM36877

Volume:

8 |

7 |

Jul 2024

Pages:

Publication Frequency:

Monthly (12 issues per year)

DOI
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10.55041/IJSREM36877

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

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Authors

JK

Jiya Kumari

PSN

Prof. Sandip Nemade

DDJ

Dr. Divya Jain

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Abstract

Image corruption during the acquisition and transmission operations may be caused by a variety of disturbances. Scientists are still having trouble getting rid of the noise in the original picture. picture denoising is a technique used to improve a picture’s visual quality and extract small details from a damaged image. Improving an image to make it crisper than it was originally is the aim of image restoration. The field of image processing is vast. This paper presents the results of some significant work in the subject of image denoising. It looks into image denoising using some of the most recent methods, such as SEPD (Simple Edge Preserved De-noising) and RSEPD (Reduced Simple Edge Preserved De-noising). Image corruption during the acquisition and transmission operations may be caused by a variety of disturbances. Scientists are still having trouble getting rid of the noise in the original picture. picture denoising is a technique used to improve a picture’s visual quality and extract small details from a damaged image. Improving an image to make it crisper than it was originally is the aim of image restoration. The field of image processing is vast. This paper presents the results of some significant work in the subject of image denoising. It looks into image denoising using some of the most recent methods, such as SEPD (Simple Edge Preserved De-noising) and RSEPD (Reduced Simple Edge Preserved De-noising).

KEYWORDS

Power consumption analysis Digital logic circuits Ultra-low power Subthreshold operation Static CMOS gates

Cite This Article

Jiya Kumari, Prof. Sandip Nemade, Dr. Divya Jain, "A Review on FPGA-based Architectures for Noise Removal of Digital Images using High-Level Design," International Journal of Scientific Research in Engineering and Management, vol. 8, no. 7, Jul 2024. https://doi.org/10.55041/IJSREM36877

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Publication Date

7/30/2024

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Double-Blind Peer Review

Review Rounds: 2

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