A Review on VLSI Aspects of Error Detection and Correction on SOCs

The implementation of error detection and correction codes on system on chip (SOC) is one of the key challenges in VLSI design owing to the fact that SOCs are often limited in terms of computation power and memory. Turbo codes is a category of error detection and correction codes which have moderate complexity but exhibit a steep descent in the error floor. The name is derived from the fact that two decoders try to simultaneously decode the encoded sequence of bits synonymous with the turbo engines. This paper presents a VLSI perspective and comprehensive review on need of error detection and correction. The emphasis has been laid on the error detection and correction employing the turbo encoding mechanism. The turbo encoding mechanism has been chosen as the baseline technique as it shows adherence to the Shannon’s limit while exhibiting a steep plummet in the error rate, in the error rate even at low SNR values. The important features of the turbo encoding-decoding process has been cited with explanations. A review of the various categories of turbo codes and similar approaches has been presented. Salient features of contemporary work have been cited.