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ArticlePeer ReviewedOpen AccessPlagiarism Passed
Paper ID:IJSREM37330

A Spatially Coupled Structure of Turbo codes for VLSI-SoC Applications

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-

Subject:

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Paper ID:

IJSREM37330

Volume:

8 |

9 |

Sep 2024

Pages:

Publication Frequency:

Monthly (12 issues per year)

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Not assigned

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

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Authors

MS

Mohammad Subhani

P(T

Prof. (Dr).Dolly Thankachan

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Abstract

The chip level implementation of error detection and correction codes is a challenging aspect for VLSI systems as the system complexity often makes it infeasible for systems to be implemented within the constraints of memory and processing speed. One of the most effective techniques for error detection and correction happen to be the turbo codes. The turbo codes have two encoders and two decoders working in synchronization to perform the error detection and correction mechanism. In this paper, a cascading and sharing of bits is proposed to implement error detection and correction in systems which can be implemented on system on ship (SoC). It has been shown that the proposed system attains lesser error rate at moderate iterations as compared to exiting research work.

KEYWORDS

SoC Error Detection and Correction VLSI iterations cascaded bits.

Cite This Article

Mohammad Subhani, Prof. (Dr).Dolly Thankachan, "A Spatially Coupled Structure of Turbo codes for VLSI-SoC Applications," International Journal of Scientific Research in Engineering and Management, vol. 8, no. 9, Sep 2024.

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Publication Date

9/20/2024

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Review Rounds: 2

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The authors declare no conflict of interest related to this research work.

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