A VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter

A FIR filter is used in digital signal processing to eliminate undesirable components or noise from a signal. In order to efficiently eliminate noise from the received channel data bits, this work presents the VLSI architecture of a Multi-Standard Digital Up Converter (DUC) based FIR filter. In the accumulation unit’s existing architecture, carry skip addition was utilized. Shift add architecture is used in this proposed architecture to achieve an efficient adaptation delay, area, and power implementation. The architecture is designed using Carry look ahead adder, which is used in the accumulation unit. The results demonstrate that the proposed technique produces less area and power consumption than the existing DUC based RRC filter architecture. In this project, the suggested filter is implemented using the VERILOG programming language in Xilinx ise 14.7. In this project, the FIR filter’s VERILOG coding is used, and simulation is used to view waveforms. The increasing need for high performance and low power DSP is a result of the multimedia applications’ rapid expansion. The RRC digital filter is the primary component of a DSP system that is most frequently employed.