AES 128 Bit Optimization: High-Speed and Area-Efficient through Loop Unrolling

AES 128 Bit Optimization: High-Speed and Area-Efficient through Loop Unrolling

Sandarbh Yadav, Gunin Girdhar,

sandarbh.yadav.ug20@nsut.ac.in , gunin.girdhar.ug20@nsut.ac.in

Department of Electronics and Communication Engineering, Netaji Subhas University of Technology (NSUT) Azad Hind Fauj Marg, Sector-3,

Dwarka, New Delhi, Delhi 110078, India

Abstract: This study introduces a high-throughput FPGA implementation of AES-128, prioritizing efficiency for robust security and fast data processing needs. AES-128 is renowned for its security and widespread use in various applications. Employing techniques like loop unrolling and pipelining, the implementation maximizes throughput and customizes AES for FPGA architectures. A novel optimization approach, "new-affine-transformation," reduces resource demands and latency for the Sub-Bytes function. The AES architecture is strategically modified for efficiency, with rearranged functions and streamlined processing. The implementation, in VHDL and utilizing Xilinx Virtex-5 FPGA, achieves remarkable performance: 37.9 Gbps (encryption) and 38.5 Gbps (decryption) throughput at frequencies of 296.789 MHz (encryption) and 300.806 MHz (decryption). Resource utilization is efficient, with 264 (encryption) and 260 (decryption) slice registers and 1044 (encryption) and 1581 (decryption) total slices.

Keywords: AES, FPGA, cryptography, encryption, decryption, throughput, plain text, cipher text