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Stream/Area:
-
Subject:
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Paper ID:
IJSREM68001
Volume:
10 |
10 |
Oct 2026
Pages:
1-5
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
Electronics and Communication Engineering
CMR Technical Campus
In modern embedded architectures and System-on-Chip (SoC) platforms, transferring data between memory blocks and peripheral interfaces is one of the most frequent operations. However, in many practical scenarios—such as wireless sensor nodes, biomedical monitors, and IoT devices—data is not generated continuously. Instead, it arrives sporadically in response to external real-world triggers. Keeping a conventional direct memory access controller continuously running or polling peripheral status registers during these idle intervals causes unnecessary clock switching and wastes precious power. To overcome this issue, this project presents the design, implementation, and verification of a compact, Event-Triggered Direct Memory Access (DMA) Mini Controller tailored for low-power SoC environments. The controller stays in a low-power quiescent state and begins moving data only after receiving an external hardware event signal (event_in). The transfer parameters—including the 32-bit source starting address, the 32-bit destination starting address, and the 16-bit transfer size—are fully programmable. A Finite State Machine (FSM) coordinates the internal operations, transitioning cleanly between idle, active transfer, and completion stages. The controller was modeled in Verilog HDL and thoroughly evaluated using the AMD Vivado Design Suite through RTL elaboration, behavioral simulation, and power estimation. The design was verified using a representative test case with a source starting address of 0x1000, a destination starting address of 0x2000, and a transfer length of 0x0004 words. The simulation waveforms confirm that the controller remains inactive prior to the event, turns active immediately upon trigger assertion, increments source and destination memory pointers accurately on each beat, and asserts a transfer-done flag upon finishing. Power analysis in Vivado reported an estimated total on-chip power consumption of 0.122 W on the target FPGA platform. This lightweight architecture offers an effective, easily extensible hardware building block for event-driven, power-conscious digital systems.
KEYWORDS
Power analysis was performed in AMD Vivado for the tested design configuration. The supplied Vivado result reports approximately: Total on-chip power = 0.122 W This value represents the estimated power reported for the particular configuration used during the project evaluation. It should not be treated as a universal power value for every FPGA device or operating condition because power depends on factors such as device selection, clock frequency, switching activity, constraints, and implementation settings. The purpose of including the power result is to provide an implementation reference for the present design. A direct comparison of power savings would require measurements under the same conditions for a conventional design and the event-triggered design.
[1] L. Benini, A. Bogliolo, and G. De Micheli, “Dynamic power management of electronic systems,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1998, pp. 696–702, doi: 10.1145/288548.289120. [2] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473–484, Apr. 1992, doi: 10.1109/4.126534. [3] L. Benini, A. Bogliolo, and G. De Micheli, “A survey of design techniques for system-level dynamic power management,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 3, pp. 299–316, Jun. 2000, doi: 10.1109/92.845896. [4] T. Kitahara, F. Minami, T. Ueda, K. Usami, S. Nishio, M. Murakata, and T. Mitsuhashi, “A clock-gating method for low-power LSI design,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 1998, doi: 10.1109/ASP-DAC.1998.669476. [5] L. Benini and G. De Micheli, Dynamic Power Management: Design Techniques and CAD Tools. Boston, MA, USA: Kluwer Academic Publishers, 1998, doi: 10.1007/978-1-4615-5455-4. [6] J. M. Rabaey, A. P. Chandrakasan, and B. Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd ed. Upper Saddle River, NJ, USA: Prentice Hall, 2003. [7] Arm Ltd., “AMBA specifications: AXI, AHB, APB, and low-power interfaces.” [Online]. Available: https://www.arm.com/architecture/system-architectures/amba/amba-specifications. Accessed: Oct. 14, 2026. [8] IEEE, IEEE Standard for Verilog Hardware Description Language, IEEE Std 1364-2005, Apr. 2006, doi: 10.1109/IEEESTD.2006.99495. [9] AMD, Vivado Design Suite User Guide: Power Analysis and Optimization, UG907. [Online]. Available: https://docs.amd.com/r/en-US/ug907-vivado-power-analysis-optimization. Accessed: Oct. 14, 2026. [10] “A comprehensive survey of clock-gating techniques for low-power VLSI design,” in Proceedings of the 2025 9th International Conference on Electronics, Communication and Aerospace Technology (ICECA), Nov. 2025, doi: 10.1109/ICECA66444.2025.11383489.
Publication Date
10/15/2026
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
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