Analysis of Low power and high performance of mixed losgic line

Analysis of Low power and high performance of mixed losgic line

Prof. Sachin Singh1, Prof. Rakesh Mishra2, Ekta Sahu3

1Electronics &Communication Deptt , SRIST Jabalpur

2Electronics &Communication Deptt , SRIST Jabalpur

3Electronics &Communication Deptt , SRIST Jabalpur

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Abstract -—The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.

Key Words:Decoders, Mixed Logic design , Power and Delay Optimization I