Analysis of Low Power High Speed Parallel Prefix Adder Using Cadence Encounter Platform

Analysis of Low Power High Speed Parallel Prefix Adder Using Cadence Encounter Platform

Ravi L S a*, Sinchana H S b*, Thejaswini A R c*, Tulasi C S d* Vinutha N Ae*

a Assistant Professor, Department of Electronics and Communication, Rajeev Institute of Technology, Hassan-573201,India

b,c,d,e Students, Department of Electronics and Communication, Rajeev Institute of Technology, Hassan-573201,India

I.                ABSTRACT

High performance in the age of lightning-fast computing and energy-efficient electrical devices depends on the creation of optimised arithmetic units.  The efficiency of adders, which are crucial components of the majority of digital systems, has a direct effect on the system's overall speed and power usage. In this study, a low-power, high-speed parallel prefix adder (PPA) architecture leveraging Cadence nclaunch is designed and implemented.  In terms of gates, power, and area, prefixes topologies such as Brent-Kung and Kogge-Stone are examined and contrasted. The suggested architecture uses effective gate-level implementations and logic-level optimisations to lower power consumption without sacrificing speed. To confirm functionality and performance, the design is synthesised and simulated using the cadence tool. When compared to traditional adder architectures, the findings show a notable gain in both power efficiency and area, demonstrating the usefulness of the suggested integration strategy in contemporary low-power, high-speed VLSI systems.

Keywords: PPA, EDP, SoC, FPGA.