Analysis of Vivado Implementation Strategies Regarding Side-Channel Leakage for FPGA-Based AES Implementations.

Analysis of Vivado Implementation Strategies Regarding Side-Channel Leakage for FPGA-Based AES Implementations.

Hulimani Manju Bhashini1 Dept of ECE IARE

Dr. S China Venkateshwarlu2 Professor Dept of ECE IARE

Dr. V Siva Nagaraju3 Professor Dept of ECE IARE

 Ms. P Ganga Bhavani4 Assist. Professor Dept of ECE IARE

DOI: 10.55041/IJSREM48689

Abstract - Dynamic restructuring of cryptographic implementations has been proposed as a viable countermeasure against power and electromagnetic-based Side Channel Attacks (SCA). These kinds of countermeasures involve shuffling between functionally identical but structurally different realizations (known as variants) of a cryptographic circuit using Partial Reconfiguration. Previous studies show that the overall resistance of this countermeasure relies on the strength of individual variants. In this work we explore the possibility to use AMD Xilinx Vivado’s implementation strategies to easily generate variants and evaluate their influence on the resistance of AES against SCA using various metrics. For different implementation strategies, we present leakage behavior for individual bits of the resulting AES realizations and also their impact on overall resistance against SCA.

Key Words : AES Encryption, FPGA Implementation, Side-Channel Leakage, Vivado Design Suite, Power Analysis Attacks, Electromagnetic Analysis, Timing Attacks, Hardware Security, Cryptographic Countermeasures, Masking Techniques, S-box Protection, Clock Jittering, Noise Insertion, High-Level Synthesis (HLS), IP Integrator, Floor planning, Resource Utilization, Performance Optimization, RTL Design, Secure FPGA Design.