Area and Power Optimized 8×8 Truncated and 8×8 Array Multiplier Using Hybrid 1 Bit Full Adders

Multiplication is a fundamental operation in digital signal processing (DSP), neural network accelerators, and embedded systems. Conventional parallel multipliers offer high performance but incur considerable area and power overhead, especially in deep submicron VLSI technologies. Truncated multipliers and Array multipliers are reducing hardware cost by omitting least significant partial product columns but introduce accuracy degradation. This paper proposes an area and power optimized 8×8 truncated and 8×8 array multiplier architectures employing hybrid 1‑bit full adders implemented 90nm CMOS technology. The hybrid full adder utilizes a combination of transmission‑gate and pass‑transistor logic to achieve full‑swing outputs with reduced transistor count. Variable‑correction logic is integrated to compensate for removed partial products, enhancing accuracy while maintaining low hardware cost. Tanner EDA simulations demonstrate that the proposed architectures are achieve up to 27.2% area reduction and up to 57% power savings for the 1‑bit adder, along with 9% power savings for the truncated multiplier compared to conventional full‑adder‑based designs. The proposed design is therefore well suited for DSP cores, filtering engines, and energy‑efficient computing units.