Area and Power Optimized VLSI Architecture of Approximate Multiplier

Area and Power Optimized VLSI Architecture of Approximate Multiplier

Ratnala Geethika, K Kavya

M-Tech in VLSI and Embedded Systems, Department of Electronics and Communication Engineering, Sanketika Institute of Technology and Management

Assistant Professor, Department of Electronics and Communication Engineering, Sanketika Institute of Technology and Management

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Abstract - When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. This brief discusses an innovative design technique for approximating multipliers. When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. Within the scope of this short, a unique 4-2 approximate compressor is presented. This compressor is complimentary to existing compressors that have been developed in previous work. Additionally, A proposed multiplier is built using the compressors, a constant approximation, and error correction. The simulation results show that the designed approximation multiplier performs satisfactorily. Within the Xilinx-Vivado environment, the implementation, synthesis, and simulation are carried out and recorded using the verilog HDL programming language.

Key Words:  approximate multiplier, exact compressor, approximate compressor and Verilog HDL.