BUILT-IN-SELF-TEST USING WEIGHTED TRUE RANDOM PATTERN GENERATOR

This work presents a Weighted True Random Pattern Generator (WTPG) integrated with a Built-In Self-Test (BIST) architecture to improve digital circuit testing. By combining true randomness with a controllable weighting mechanism, the proposed design generates high-quality test patterns that enhance fault coverage and detect complex faults more effectively than conventional methods. The system also reduces test time, hardware overhead, and dependence on external testing equipment. Its scalability and efficiency make it well suited for modern VLSI and System-on-Chip (SoC) applications, providing a reliable solution for next-generation digital circuit testing

[1] P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques. New York, USA: Wiley, 1987. [2] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Boston, MA, USA: Springer, 2000. [3] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability. San Francisco, CA, USA: Morgan Kaufmann, 2006. [4] J. Savir, “Survey of stochastic testing,” IEEE Transactions on Computers, vol. 33, no. 10, pp. 933–940, Oct. 1984. [5] S. Wang and S. K. Gupta, “DS-LFSR: A new BIST TPG for low heat dissipation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 842–850, Jul. 2002. [6] X. Kavousianos, K. Chakrabarty, and D. Nikolos, “Test data compression for scan-based BIST using weighted random patterns,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 11, pp. 1979–1992, Nov. 2008. [7] M. Tehranipoor and N. Ahmed, “Low-power test pattern generation for BIST,” IEEE Design & Test of Computers, vol. 24, no. 6, pp. 542–553, Nov.–Dec. 2007. [8] B. Sunar, W. J. Martin, and D. R. Stinson, “A provably secure true random number generator with built-in tolerance to active attacks,” IEEE Transactions on Computers, vol. 56, no. 1, pp. 109–119, Jan. 2007. [9] M. Bucci and R. Luzzi, “Design of testable random bit generators,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2005, pp. 2751–2754. [10] A. T. Markettos and S. W. Moore, “The frequency injection attack on ring-oscillator-based true random number generators,” in Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES), 2009, pp. 317–331.