Comparative Analysis of 8-Bit Test Pattern Generator for LBIST

Comparative Analysis of 8-Bit Test Pattern Generator for LBIST

Jasha Varma B1, Ushashree V2, Shantha Mahantha Gouda Goudar3, Sumangala G Chulaki4

1Department of Electronics and Communication, Ballari Institute of Technology and Management

2Department of Electronics and Communication, Ballari Institute of Technology and Management

3Department of Electronics and Communication, Ballari Institute of Technology and Management

4Department of Electronics and Communication, Ballari Institute of Technology and Management

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Abstract - In order to guarantee their dependability, modern integrated circuits require efficient testing techniques. One of the greatest DFT methods [2] for logic design when an IC must be tested on a regular basis is LBIST. The DUT, a comparator, an analyzer, a test pattern generator, and memory for storing golden values are all part of the LBIST architecture. DUT affects the circuit's power because it dwells with the test circuitry. The use of area- and power-efficient TPG can lower this overhead. The project's primary goal is to put several TPGs that have been presented in a lifetime into practice and conduct a comparative analysis of them.

Key Words:  DFT, CUT, ORA, MC-LFSR, BSMCS, BS-LFSR, LP-TPG.