Comparative Performance Evaluation of Different 8-Bit Approximate Multipliers for Computer Vision Applications

A unique14-point FPGA timing sweep was planned to compare the exact, ordinary truncated, fixed-bias, and BWC-3 8-bit multipliers using integrated wrapper. The measurements reveal a clear trade-off among timing robustness, and implementation hardware cost. The ordinary truncation multiplier is the smallest design and meets timing at 200 MHz, fixed bias also preserving 200-MHz timing closure and retaining lower LUT, dynamic-power, PDP, and ADP values compare with the exact reference. The BWC-3 architecture have the highest arithmetic accuracy, but its additional compensation logic limits measured timing closure to 133 MHz and increases LUT/ADP cost for hardware. For high-throughput vision architecture datapaths, the observed data thus identified fixed bias as a balanced implementation point, while BWC-3 is better for accuracy demanding operations.

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