Comparison of Adder Architectures and Design of a Modified Low-Power Energy-Efficient Parallel Prefix Adder

– With the growing need for efficient digital circuits, particularly in processors and communication networks, there arises a need to design arithmetic units that are low in power and energy usage. These adders play a very significant role in determining not only performance but also the power consumed and the area. This work focuses on comparing some conventional adder designs with those of the parllel prefix adders with regard to delay, power, number of Transistors and Energy. From this comparative analysis, an innovative design of a low power and energy efficient parallel prefix adder is developed. The innovation involves making certain design changes in the prefix operation and carry propagation process, as well as implementing low-power measures through the Low power techniques like logic Reconstruction. All adders are modeled and simulated using standard CMOS technology library in Cadence tools (65nm technology) based on delay, power, number of Transistors and Energy. The simulation shows that the proposed design of the low power, energy efficient PPA provides significant reduction in power while retaining good speed.