Complex Test Pattern Generator (CTPG)-an extension of ATPG and its Application for Highly Compacted Test Sets

Complex Test Pattern Generator (CTPG)-an extension of ATPG and its Application for Highly Compacted Test Sets

Tulika Saha, Shivani Mishra, Aditya Ranjan Roy

Abstract— Integrated chips or System on chip devices act as the backbone for numerous evolutions in the currently growing technology world. Integrated ICs are helpful to store massive data, to process it effectively, to formulate the compact memory for multi-tasking systems. Soc devices need to be tested before evaluating a digital architecture bare chip testing is applicable in most of the core development platforms where the system on ship platform undergoes various test processes to check the Silicon level fabrication quality before developing a Digital circuit in it. The proposed system is focused on creating an inbuilt test platform with reconfigurable architecture and optimised test pattern generation model to make the soc validation more accurate. The presented system not only focused on optimising the test patterns but also provided a Complex test set to solve the problems in test modules. Here Complex pattern test generator with enhanced version of built-in self-test is implemented. The presented system is analysed by comparing the performance of the developed test model with various FPGA platforms in terms of power area utilisation and latency.

Keywords— Low power design, System on chip (SoC), Built in self-test (BIST), automatic test pattern, soc validation.