Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation

Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation

B. Kanth Naga Ayyappa1 Dept of ECE IARE

Dr. S China Venkateshwarlu2 Professor Dept of ECE IARE

Dr. V Siva Nagaraju3 Professor Dept of ECE IARE

Abstract - The rapid growth of AI and data-intensive applications necessitates energy-efficient and high-performance memory solutions. In-memory computing (IMC) offers a paradigm shift by reducing data movement and enabling computation directly within memory arrays. This work presents a Compute SNDR-Boosted (Statistical Noise and Defect Resilience) 22-nm MRAM-based IMC macro that leverages statistical error compensation to mitigate device-level variability and noise. Our method integrates a statistical correction engine, enhancing the Signal-to-Noise and Distortion Ratio (SNDR), thereby achieving high accuracy, robustness, and energy efficiency in IMC operations.

Key Words:  MRAM, In-Memory Computing, SNDR, Statistical Error Compensation, 22nm Technology, Hardware-Aware Machine Learning, Compute-in-Memory (CIM)