Design and Analysis of 32-bit Arithmetic Logic Unit using Reversible Logic Gates

The most crucial component of any microprocessor, computer, and digital signal processor (DSP) is the ALU. The processor’s arithmetical and logic unit handles all logical and arithmetic operations. The complexity of the internal logic determines the CPU’s processing speed. Analysing the error point gets more difficult while implementing ALU using irreversible gates. Using reversible gates for Arithmetic Logic Unit (ALU) is a potentially useful method for reducing energy dissipation in computer architecture. Traditional ALUs, constructed with irreversible logic gates, face challenges related to energy efficiency, particularly in power-constrained environments. Reversible computing offers a solution by ensuring that computational steps are reversible, thus theoretically conserving energy. Since the input and output vectors in reversible logic gates are mapped one to one, input state vectors may always be rebuilt from output state vectors. Reversible logic circuits are capable of operating in both forward and backward directions. The ALU gives the computer the ability to add, subtract, and carry out logical operations like AND, OR, and so on. The proposed ALU is made up from Peres, Feynman, & Fredkin reversible gates. Initially a 8-bit ALU is designed by using these gates, then the 8-bit ALU’s are integrated to form the 32-bit ALU. The proposed ALU performs arithmetic (addition, subtraction) and logical operations (AND, OR, NAND, NOR, XOR, XNOR), demonstrating the effectiveness of reversible logic for low-power computing.