Design and Analysis of a Quantum Random Number Platform

A pseudorandom bit generator (PRBG) is a crucial element in ensuring the security of data during its transmission and storage in different cryptographic applications. Out of the commonly used techniques for generating pseudorandom numbers, including linear feedback shift register (LFSR), linear congruential generator (LCG), connected LCG (CLCG), and dual-coupled LCG (dual-CLCG), the dual-CLCG approach is shown to be more safe. This approach utilizes in equality comparisons to generate pseudorandom bits at regular intervals. Therefore, a novel design of the dual- CLCG technique is created, which produces pseudo-random bits at a consistent clock rate. This work proposes a novel approach termed “modified dual-CLCG” for pseudo- random bit generation (PRBG) together with a very large-scale integration (VLSI) architecture. The purpose of this method is to address the aforementioned concerns. The innovative feature of the proposed PRBG approach is its ability to create pseudorandom bits at a consistent clock rate, with just one initial clock delay and little hardware complexity.