Design and Analysis of Negative Capacitance FET based 6T SRAM Cell for Next generation low-power Applications

Design and Analysis of Negative Capacitance FET based 6T SRAM Cell for Next generation low-power Applications

1 Padala Kavya
UG Student

ECE Department

GMR Institute of   Technology

Rajam, India

kavyapadala2003@gmail.com

2M.Shanmukeswar Rao

UG Student

ECE Department GMR Institute of Technology

Rajam, India

shanmanthripragada@gmail.com

3 Nagara Pooja
UG Student

ECE Department

GMR Institute of Technology Rajam, India

nagarapooja1234@gmail.com

Abstract— Power optimization has become increasingly critical in the VLSI industry due to the rising density of memory systems, which leads to higher power consumption. Static RAM (SRAM) cells are particularly affected by this issue. A significant contributor to power consumption is the leakage current in transistors. Therefore, decreasing power consumption in each memory cell is essential. This paper focuses on optimizing the power of various 6T SRAM cells by employing advanced techniques like power gating, reverse biasing, and transistor stacking in the context of Negative Capacitance Field-Effect Transistors (NCFETs).

    Keywords—SRAM, NCFET, power consumption, power gating,

Delay, Transistor Stacking