Design and Development of 1×3 Router

“Design and Development of 1x3 Router”

Skandha S Bhat

Department of Electronics and Communcication BMS College of Engineering

Bangalore, India skandhas.ec21@bmsce.ac.in

Sonali Nilesh Ghode

Department of Electronics and Communcication BMS College of Engineering

Bangalore, India sonali.ec21@bmsce.ac.in

Shashank A

Department of Electronics and Communcication BMS College of Engineering

Bangalore, India shashanka.ec21@bmsce.ac.in

Mrs. Sowmya Sunkara, Assistant Professor Department of Electronics and Communcication BMS College of Engineering

Bangalore, India

sowmi.ece@bmsce.ac.in

Abstract— In modern Network-on-Chip (NoC) architectures, efficient data routing is essential for high-speed and scalable communication. This paper presents the Register Transfer Level (RTL) design and synthesis of a 1x3 router tailored for such applications. The 1x3 router features one input port and three output ports, and is designed to manage data packet traffic with minimal latency and optimized area utilization. The design process involves the development of key components including the FIFO buffer, arbiter, and control logic, modeled in Verilog HDL. Functional verification is conducted through simulation using Xilinx ISE tools, and synthesis is carried out to assess timing, area, and power characteristics. The results confirm the design’s efficacy in meeting performance goals, demonstrating its potential for integration into larger NoC systems. This work lays the groundwork for future enhancements in router scalability and adaptability for complex SoC environments.

Keywords— RTL Design, 1x3 Router, Verilog HDL, FIFO Buffer, Finite State Machine (FSM), Cadence Genus, Cadence Xcelium, Logic Synthesis, Network-on-Chip (NoC), VLSI Design, Low Latency Routing, Digital Communication Systems, Hardware Verification, Gate-Level Netlist, ASIC Design.