Design and Development of UART Protocol Using Verilog with UVM Testbench

Design and Development of UART Protocol Using Verilog with UVM Testbench

Krushna K. Chavan1, Shreya S. Kirdak1 , Aboli S. Bhagwat1 , Snehal R. Sabale2, Ajit Gangad2

1B.E-Electronics & Telecommunication Engineering/Student, Vidya Pratishthan's Kamalnayan Bajaj Institute of Engineering and   Technology, Baramati, India

2M.E-Electronics & Telecommunication Engineering/Assistant Professor Vidya Pratishthan's Kamalnayan Bajaj Institute of Engineering and Technology, Baramati, India

Email address: krushnachavan2310@gmail.com (Krushna K. Chavan)   snehal.sabale@vpkbiet.org (Snehal R. Sabale)

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Abstract –

This paper's primary goal is to use Verilog (V) to design and validate a full duplex UART module. The Universal Asynchronous Receiver/Transmitter, or UART, is a two-way transmission channel that not only significantly increases the efficiency of information transfer between computers and external devices but also guarantees information accuracy and consistency through the use of baud rate settings, the elimination of metastable state, and other techniques. In this work, the definition and operation of UART are well understood, and the UART is constructed using the Verilog HDL language, EDA simulation, picture, and data. The findings of the experiment demonstrate that this module's sending and receiving module functions well and satisfies the specifications of full-duplex serial communication equipment. Without a doubt, the layout of this paper has made the fundamental working concept of UART more clearly explained, which will aid in its future.

Key Words:- UART, EDA , BRG, IC, DUT, UVM