DESIGN AND FPGA IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER

This paper awaits the design of the Vedic Multiplier using the Ancient Indian Technique known as the Vedic Mathematics modified to improve the performance of processors. Processor performance is highly dependent on the frequency used which is one of the Basic hardware block in most processing systems. This paper describes the design of a powerful 8-bit fast-paced architecture using the Urdhva – Triyakbhyam Sutra Vedic method of repetition. This 8-bit multiplier is designed using four 4-bit multipliers and 3 Ripple Carry Adders. This 8-bit Vedic Multiplier was coded with VHDl integrated and copied using Xilinx software ISE14.2 and performed the same on FPGA (Spartan 3E).