Design and High Performance Evaluation of a Low Power Bit-Line SRAM PMOS Biased Sense Amplifier

Design and High Performance Evaluation of a Low Power Bit-Line SRAM PMOS Biased Sense Amplifier

Kalla Sandhya1, Cheepurupalli Krishna Chaitanya1, Javapu Sai Kumar2 , Pulamarasetti Vani2, Gandi Swathi 2,Surisetti Balakrishna2, Geddam Gowri2

1Assistant Prof., Dept. of ECE, Visakha institute of engineering and technology, Vizag, India

2Student, Dept. of ECE, Visakha institute of engineering and technology, Vizag, India

1kallasandhya96@gmail.com, 1krishnachaitanyach4@gmail.com

2saikumarjavapu953@gmail.com 2vanipolamarasetty2002@gmail.com, 2gandiswathi333@gmail.com, 2surisettybalakrishna83408@gmail.com, 2gowrigeddam016@gmail.com

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Abstract - Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality   and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters.

Key Words:  Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.