Design and Implementation of a 3-bit ALU with Integrated 7-Segment Display on FPGA

This paper describes the design and implementation of a 3-bit Arithmetic Logic Unit (ALU) with integrated 7-segment display output, deployed on an FPGA platform. The objective of this project is to efficiently perform and display basic arithmetic and logic operations, including addition, subtraction, AND, OR, XOR, and NOT, with an FPGA-based ALU. A control signal selects the operation, and the ALU’s 3-bit result is decoded and displayed on a 7-segment interface for clear output visualization. The ALU design is coded in Verilog and includes logic to manage carry and overflow in arithmetic functions. A display decoder module maps the ALU’s binary output to the correct LED segments on the 7-segment display, allowing intuitive real-time readout of operation results. The system was synthesized, simulated, and tested on an Artix-7 FPGA using the Xilinx Vivado development environment, achieving accurate and expected functionality across all operations. This work showcases the effectiveness of FPGA technology in integrating computation and display within a compact digital system, with potential applications in both educational and embedded system design settings where real-time processing and display are essential.