Design and implementation of a 5-stage pipelined risc-v processor with hazard detection and forwarding unit using Verilog HDL

The increasing demand for high-performance and energy-efficient computing systems has created the need for advanced processor architectures capable of executing instructions quickly and efficiently. Pipelining is one of the most effective techniques used in modern processors to improve instruction throughput and maximize hardware utilization. In this project, a 5-Stage Pipelined RISC-V Processor with Hazard Detection and Forwarding Unit has been successfully designed and implemented using Verilog HDL. The proposed processor architecture consists of the five classical pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). To enhance processor performance and ensure correct instruction execution, pipeline registers were incorporated between consecutive stages. These registers enable multiple instructions to be processed simultaneously, thereby increasing instruction-level parallelism and improving overall system throughput.   One of the major challenges in pipelined processors is the occurrence of data hazards. To address this issue, a Forwarding Unit was implemented to forward data directly between pipeline stages, reducing unnecessary pipeline stalls and minimizing execution delays. In addition, a Hazard Detection Unit was integrated to identify instruction dependencies and generate stall signals whenever forwarding alone could not resolve the hazard. These mechanisms significantly improved pipeline efficiency and ensured reliable processor operation. The complete processor design was simulated and verified using Icarus Verilog and GTKWave. Simulation results demonstrated correct Program Counter operation, successful instruction fetching and decoding, proper ALU execution, accurate data propagation through pipeline registers, and successful operation of forwarding and hazard handling mechanisms. The processor correctly executed the test instruction sequence: ADDI x1, x0, 2 ADDI x2, x0, 3 ADD  x3, x1, x2 and produced the expected result: x1 = 2 x2 = 3 x3 = 5 The obtained results confirm the functional correctness of the proposed processor architecture. Compared with conventional pipelined implementations, the inclusion of forwarding and hazard detection mechanisms reduces pipeline stalls, improves instruction throughput, and enhances processor performance without significantly increasing hardware complexity. Therefore, the proposed 5-Stage Pipelined RISC-V Processor with Hazard Detection and Forwarding Unit provides an efficient and scalable processor architecture suitable for FPGA-based embedded systems, educational processor design, and advanced computer architecture research. The developed processor also serves as a strong foundation for future enhancements such as branch prediction, cache memory integration, superscalar execution, out-of-order processing, and FPGA implementation on Xilinx or Intel development boards. Key Achievements ·        Designed and implemented a complete 5-stage pipelined RISC-V processor. ·         Successfully developed IF, ID, EX, MEM, and WB stages. ·         Implemented pipeline registers for parallel instruction execution. ·         Integrated Forwarding Unit to reduce data hazards. ·         Integrated Hazard Detection Unit to improve pipeline reliability. ·        Verified processor functionality through simulation. ·         Achieved correct instruction execution and data propagation. ·         Improved processor throughput compared to basic non-pipelined architectures. ·         Developed a scalable architecture suitable for future research and FPGA implementation.

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