Design and Implementation of a MIPS-Based RISC Processor on FPGA

This paper presents the complete design, implementation, and performance analysis of a 32bit MIPS-based Reduced Instruction Set Computer (RISC) processor using FPGA toolchains. The work begins with the development of a single- cycle processor to establish fundamental datapath functionality, followed by the integration of R-type, I-type, and J- type instruction formats. To enhance throughput, a fully functional 5- stage pipelined architecture—comprising In- struction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM), and Write-Back (WB)—is implemented using Verilog HDL. Xilinx Vivado 2023.1 is used for design, simulation, and FPGA synthesis, while Cadence 45 nm technology is used for detailed timing, area, and power analysis. The design incorporates hazard detection and for- warding mechanisms to ensure pipeline correctness and minimize stalls. Experimental results confirm accurate exe- cution of all supported instruction classes, reduced propagation delay, and efficient hardware utilization. The imple- mentation demonstrates a complete academic-to-industry design flow, providing insights into processor architecture, pipelining efficiency, and low- power digital design strategies.