Design and Implementation of a Secure Voting Machine Using De-10 Nano FPGA with Verilog

Design and Implementation of a Secure Voting Machine Using De-10 Nano FPGA with Verilog

Sudheer Reddy, Tejeswararao Padda, Manoj Bande, Jahnavi Mandala, Naga Praveen Kandula

Abstract

This paper presents the design, implementation, and testing of a secure voting machine system utilizing the DE-10 Nano FPGA and Verilog programming. The system integrates an LCD for displaying results, a fingerprint sensor for voter authentication, and external push buttons for vote casting. The system was tested with 5 party candidates and 4,000 participants, demonstrating its capability to accurately count votes, display individual vote counts, and declare the winner. The voting process is controlled through an admin code, push buttons, and slide switches for mode operations. Additionally, the system calculates the total poll percentage, adding another layer of insight into voter turnout. Voter data, including fingerprints, were securely stored on an Azure Cloud platform, with the total information including all 10 fingerprints of each voter and their detailed voter information. The paper includes result images of the front-end website page and Azure cloud storage page, as well as simulation results, RTL block diagrams, related tables, and FPGA prototyping images, highlighting the system’s efficacy and potential for real-world applications.

Index Terms— Voting Machine, FPGA Prototyping, Verilog, Fingerprint Authentication, UART Protocol, Cloud Storage, Secure Voting