Design and Implementation of an 8x8 Array Multiplier using Verilog HDL for FPGA platform for DSP Applications

The current paper describes the architectural design, implementation using HDL in the Verilog language, and behavioral verification of the high precision 8X8 Array Multiplier that is used for high speed DSP applications. In the current work, the architecture uses the partial products generator which utilizes the 64 AND gates and multi operand adder based on the accumulation network which consists of 8 Half Adders and 48 Full Adders. The architectural design proposed above has been verified behaviorally by using all 65,536 (256X256) input combinations and hence achieves 100% mathematical accuracy with zero arithmetic errors.   The architecture presented here has been implemented on an FPGA platform using the Vivado Design Suite software by Xilinx Corporation. Elaboration and netlist analysis have indicated that the logic for the carry save adder circuit has successfully mapped into the 3-input Look-Up Tables (LUT3 primitives). The power consumption has been found to be 1.035W after implementation of the netlist stage. It is worth noting that the internal logic of the core circuit has only used 0.005 W (5 mW) of power.   The future work will include widening the structure to 16X16 and 32X32 bit widths, adding multi stage pipeline registers on the diagonal paths in order to increase clock frequency and using the multiplier core in real time image convolution or FIR-filter pipelines.[26], [27]

[1]  S. Asif and Y. S. Zhang, "Performance analysis of array and Wallace tree multipliers on Xilinx FPGAs," IEEE Access, vol. 8, pp. 123456–123465, 2020.  [2]     K. Bickerstaff, M. Schulte, and E. Swartzlander, "Parallel reduced-area multipliers," Journal of VLSI Signal Processing Systems, vol. 9, no. 3, pp. 181–192, Apr. 1995. [3]   A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design," IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473–484, Apr. 1992.  [4]  L. Dadda, "Some schemes for parallel multipliers," Alta Frequenza, vol. 34, no. 5, pp. 349–356, May 1965. [5]   M. D. Ercegovac and T. Lang, Digital Arithmetic. San Francisco, CA, USA: Morgan Kaufmann, 2004.  [6]   M. J. Flynn and S. F. Oberman, Advanced Computer Arithmetic Design. New York, NY, USA: Wiley, 2001.  [7]  A. K. Gupta and S. Wairya, "High performance and low power 8×8 array multiplier design using modified adder architectures," Microprocessors and Microsystems, vol. 60,pp. 136–147, Jul. 2018.  [8]  V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, "Low-power digital signal processing using approximate adders," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 124–137, Jan. 2013.  [9]  J. Han and M. Orshansky, "Approximate computing: An emerging paradigm for energy-efficient design," in Proc. 18th IEEE European Test Symposium (ETS), 2013, pp. 1–6. [10]  S. Hauck and A. DeHon, Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann, 2008.