Design and Implementation of an Efficient Distributed Arithmetic-Based FIR Filter Using Shared MAC Architecture

In Digital Signal Processing (DSP) applications, Finite Impulse Response (FIR) filters are crucial. However, traditional multiplier-based FIR filter architecture involves a large number of arithmetic blocks, resulting in increased hardware complexity and dynamic power consumption as the filter order is increased. To overcome the drawbacks of traditional FIR filter architecture, this work presents Distributed Arithmetic (DA) technique. Here, multiplier is avoided by replacing the multiplication operation with a lookup table-based operation and shift accumulate operation. In the proposed architecture, the shared MAC architecture is used in FIR filter implementation, resulting in improved efficiency with regard to hardware complexity and dynamic power consumption. The design is implemented for various tap lengths, and the performance is compared with the traditional multiplier-based FIR filter. Observations indicate that the proposed architecture is efficient regarding logic resource utilization and dynamic power consumption.