Design and Implementation of BIST Architecture for Low Power VLSI Applications using Verilog

Design and Implementation of BIST Architecture for Low Power VLSI Applications using Verilog

Kavya M P1, Bharath C M2,Bhavana D M3, Sadhana K R4, Vijayalakshmi D5

     1Assistant  Professor, 2Final year Student, 3Final year Student , 4Final year Student, 5Final year Student Department of  Electronics and Communication  Engineering,P E S Institue of  Technology and      Management,Shimoga

Abstract :A low-power Built-In Self-Test (BIST) scheme for a 32-bit multiplier, with an emphasis on enhancing fault coverage while m1inimizing power consumption. The proposed method utilizes a minimizing power usage is a key focus of the proposed approach, which employs a Linear Feedback Shift Register (LFSR) as part of its design, where the seed values are updated after every 2m 2^m 2m cycles. A counter is employed to monitor the number of cycles, facilitating this dynamic seed change. The objective is to achieve efficient power management in BIST while maintaining high fault detection capabilities. Different pattern generation methods are evaluated based on their power consumption. An mmm-bit binary counter and a Gray code generator  are  used  in  this  processFault detection is carried out through signature analysis using a Multiple Input Signature Register (MISR), which identifies defects in the Circuit Under Test (CUT), specifically a Vedic multiplier. The design is simulated and implemented using Xilinx ISE and a Virtex 5 Field Programmable Gate Array (FPGA), with results provided for comparison.

Key Terms: 32-bit multiplier, test pattern generation, MISR, CUT, FPGA, BIST, low-power LFSR (LP-LFSR), switching activity.