DESIGN AND IMPLEMENTATION OF CRC BASED CRYPTOGRAPHY USING FPGA FOR SECURED DATA COMMUNICATION

. For data transmission accuracy, combine CRC error detection with AES encryption. In this method, cypher text is produced by first encrypting the data with AES. The cypher text is next subjected to a CRC checksum calculation, yielding a tiny value that is attached to the end of the cypher text. The message is then transferred or stored in its entirety, including the checksum. The recipient of the message must first decrypt it using the same AES key that was used to create the message’s original plain text. Then they compare the decrypted message’s CRC checksum to the checksum that was originally transmitted with the message. The recipient can be sure that the message was sent correctly if the two checksums match. If the checksums do not match, the receiver knows that an error has occurred during transmission or storage of the message. The receiver is aware that an error occurred during message transmission or storage if the checksums do not match. In the AES Design unit, CRC is utilised in place of standard Key Generation to create keys. TRNG (True Random Number Generators) replacement has improved performance in terms of area and delay. Data encryption is now substantially more secure thanks to the enhanced encryption standard algorithm. To create a random integer or key for use in AES encryption or decryption, CRC is used in AES. dependable. error-free. This Design is implemented using Verilog HDL and simulated by Xilinx Vivado and synthesized by Xilinx tool. CRC can be used in cryptography to ensure that encrypted data is transmitted without corruption and that the resulting decrypted data is accurate and reliable.