Design and Implementation of Energy Efficient Compact Approximate Multiplier for Error-Resilient Applications

This paper aims to improve system efficiency using approximate computing by introducing optimized 4:2 compressor designs based on 8 and 20 transistors. These compressors, implemented using CMOS technology, apply constant and conditional approximation strategies to reduce computational errors without relying on error correction mechanisms. The 20-transistor version offers better accuracy with a minor increase in hardware area. Overall, the proposed multiplier architecture achieves up to 50% area savings and a 93% enhancement in the power-delay product when compared to traditional exact multipliers.