Crossref DOIMemberCiteFactoropen accessissn
SJIF Impact Factor 8.659 | ISSN: 2582-3930
IJSREM Logo

International Journal of Scientific Research in Engineering and Management

(Gateway to Global Scholars - An International, Scholarly, Multi-Disciplinary, Open Access Journal)

Peer-Reviewed Journal Designed to Meet UGC's Quality Parameters

HomeCurrent IssuePast IssuesPay OnlineConferencesEditorial BoardAbout UsContact Us
IJSREM

Loading article...

Follow Us

  • Google Scholar
  • ResearchGate
  • Academia.edu
  • Mendeley
  • LinkedIn
  • Facebook
  • Instagram

Journal Policies

  • Peer Review Policy
  • Publication Ethics
  • Copyright Infringement
  • Refund & Cancellation Policy
  • Terms and Conditions
  • Privacy Policy

Journal Identifiers & Licenses

  • ISSN Verified: 2582-3930ISSN Verified: 2582-3930
  • Crossref DOI: 10.55041Crossref DOI: 10.55041
  • SJIF Ranking: 08.659SJIF Ranking: 08.659
  • Licensed under CC BY 4.0Licensed under CC BY 4.0
  • ISO Certification: 9001:2015ISO Certification: 9001:2015
  • Indexed & Cited In: Google ScholarIndexed & Cited In: Google Scholar

Contact Us

International Journal of Scientific Research in Engineering and Management (IJSREM)

#62/1, New No 7, 1st Cross, 2nd Main, Ganganagar, R T Nagar, Bangalore North, Bangalore, Karnataka, India – 560032
[email protected]+91 93911 67991
logos
logos
Working Hours

Mon – Sat: 9:00 AM – 6:00 PM

Sunday: 10:00 AM – 4:00 PM

+91 93911 67991

© 2026 IJSREM – International Journal of Scientific Research in Engineering and Management. This is an open-access journal. Articles are published under the Creative Commons Attribution (CC BY 4.0) License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

DisclaimerPrivacy PolicyTerms and Conditions
ArticlePeer ReviewedOpen AccessPlagiarism Passed
Paper ID:10.55041/IJSREM39897

Design and Implementation of FPGA Based Optimized Multicore Processors

Stream/Area:

-

Subject:

-

Paper ID:

10.55041/IJSREM39897

Volume:

8 |

12 |

Dec 2024

Pages:

Publication Frequency:

Monthly (12 issues per year)

DOI
Digital Object Identifier
10.55041/IJSREM39897

License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.

Share this article:

Authors

KN

Kodela Navya

KB

Kammari Bhanuprasad

VS

Vangala Saicharan

DB

Dr.Prashant Bachanna

Author Services & Downloads

Full Articles

Abstract

The rapid development of system-on-chip (SoC) architectures has led to increasingly complex systems facing issues such as multi-threading failures and potential failures. To address these issues, the project announced the development of a multi-student design that combines machine learning algorithms and strong cryptographic techniques to improve performance and security. Data integrity, authentication, and encryption/decryption using private and public cryptographic keys. Use advanced cryptographic algorithms such as Secure Hash Algorithm (SHA- 256) and Advanced Encryption Standard (AES) to strongly protect sensitive data. These measures ensure data integrity while also preventing unauthorized access. Exchange data on multi-core processor architecture and peripheral devices. This setting optimizes system performance, making the system suitable for real-time and mission-critical applications. Using these resources, the architecture can be efficient in machine learning while maintaining high performance. This integration allows for detection of data changes between hardware and software to ensure seamless operation and interoperability within the system. The best in security, high performance, and flexibility across the enterprise.

KEYWORDS

AHB protocol clock register FPGA machine learning support vector machine automotive electronics design.

Cite This Article

Kodela Navya, Kammari Bhanuprasad, Vangala Saicharan, Dr.Prashant Bachanna, "Design and Implementation of FPGA Based Optimized Multicore Processors," International Journal of Scientific Research in Engineering and Management, vol. 8, no. 12, Dec 2024. https://doi.org/10.55041/IJSREM39897

Full Article/Conclusion

References

Editorial & Review Transparency

Publication Date

12/21/2024

Peer Review Type

Double-Blind Peer Review

Review Rounds: 2

Documents

Review Report (Confidential)
Copyright Form (Office)

Article Metrics & Impact

Article Views

0

Total views since publication

PDF Downloads

5

Total downloads since publication

Geographic Reach

5

Indexing, Archiving & Preservation

Google Scholar
Academia
ResearchGate
Crossref
SSRN
Semantic Scholar
Thomson Reuters
WorldCat
Mendeley
OpenAlex
EBSCO
Zenodo

Digital Preservation: This article is permanently archived on Zenodo and complies with all data preservation standards across major indexing platforms.

Ethics, Compliance & Transparency

Plagiarism Screening

This manuscript has been checked for plagiarism using TurnitinPlagiarismChecker software.

Conflict of Interest

The authors declare no conflict of interest related to this research work.

Funding Information

No funding information available for this research.

Similar & Recommended Articles

Similar Articles by Topic

Related research in the same subject area

Loading similar articles...