Design and Implementation of High Speed Hybrid Full Adder Using 16nm Technology Through Mentor Graphics

Using Pass Transistors (PTs), Transmission Gates (TGs), and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic, a new hybrid full adder architecture is given. The Mentor Graphics toolset has been used to analyse the circuit’s performance. Twenty current FA circuits have been examined using the performance parameters for comparative analysis. In order to verify the scalability of the proposed FA, word lengths up to 64 bits have been included. Only the proposed FA and five of the current designs can function at expanded to 64 bits without using a buffer in between phases. The suggested design exhibits noteworthy performance in power consumption and delay, which accounted for low power delay product, according to simulation findings.According to the simulation findings, the suggested hybrid FA circuit is a compelling option for the data route design of contemporary high-speed Central Processing Units.