Design and Implementation of High-Speed Modified Carry Select Adder Using Sklansky-Based Conditional Sum Adder

In this paper, a Sklansky-based Conditional Sum Adder (S-CSA) is introduced to enhance the performance of the Carry Select Adder (CSLA) architecture. The Sklansky adder utilizes a parallel prefix structure with minimal logic depth, enabling faster carry computation compared to conventional prefix adders such as Kogge-Stone and Brent-Kung. The conditional sum technique precomputes sum and carry values for possible input carry conditions, significantly reducing carry propagation delay during final selection. By combining the advantages of the Sklansky prefix network and the conditional sum approach, the proposed CSLA architecture minimizes redundant logic while maintaining high computational speed. The proposed S-CSA-based CSLA is designed and evaluated using standard VLSI design metrics including delay, power consumption, area, and power-delay product (PDP). Simulation results obtained using Xilinx Vivado on the Spartan-7 FPGA demonstrate that the proposed architecture achieves reduced area (127 LUTs vs. 225 LUTs), lower power (49.689 W vs. 51.065 W), and improved delay (9.835 ns vs. 12.229 ns) compared to the Brent-Kung based CSLA. The results confirm that the Sklansky-Conditional Sum Adder provides a superior trade-off among speed, area, and power, making it well-suited for high-performance and low-power VLSI applications.