DESIGN AND IMPLEMENTATION OF REVERSIBLE VEDIC MULTIPLIER WITH USING BVF, BME GATE, CNOT GATE, AND PERES GATE

Vedic Multiplier is one of the best solutions which are capable of performing the quicker multiplications by eliminating the unwanted steps in the multiplication process. In this work, the reversible Vedic multiplier with the reversible logic gates of BVF, BME, PERES and CNOT has been implemented in Vedic multipliers of various sizes has been simulated. The performance metrics of power, delay, and the area has been measured with the synthesis result and simulation result. The simulation results, observed for all the variations of bits and performance metrics of various prevailing and anticipated method. The result shows that the proposed work obtains the Garbage Outputs of 5, Constant inputs (CI) of 5 of Gate Counts (GC) of 5, Quantum cost (QC) of 17 and TRILC value of 32.

 1.       Bhagyalakshmi. H. R, and Venkatesha. M. K, “Optimized Multiplier Using Reversible Multi-Control Input Toffoli Gates”, International Journal of VLSI Design & Communication Systems, 2016, Vol. 3, No.6, 27-40. 2.       Mamataj. S, Das. B, and Rahaman. A, “A More Effective Realization of BCD Adder By Using a New Reversible Logic”, International Journal of Computational Engineering Research, 2014, Vol. 4, No. 2, 13-19. 3.       Praveena. M, and Thanushkodi. K, “A Novel Design of Reversible BCD Adder with Reduced Delay”, European Journal of Scientific Research, 2012, Vol. 83, No.2. 4.       Sarker. A, Bose. A, and Gupta.S, “Design of a Compact Fault-Tolerant Adder/Subtractor Circuits Using Parity Preserving Reversible Gates”, 17thInternational Conference on Computer and Information Technology, 2014, 1-7. 5.       Patil, Hemangi, and Sawant, "Design and Implementation of Vedic Algorithm using Reversible Logic Gates," International Journal of Engineering and Computer Science, 2015, No. 08. 6.       Narendra, Chandra shekar, “Optimization Of Delay By Using Reversible Logic Compressor Based Vedic Multiplier”, International Journal Of VLSI Design And Data Communication, 2016, Vol 4. 7.       Srikanth., and Nasam Sai Kumar, "Design of High speed low power reversible Vedic multiplier and reversible divider", International Journal of Engineering Research and Applications, 2014, Vol 4. 8.       Anitha, Neha Deshmukh, Prashant Agarwal, Sarat Kumar Sahoo, Prabhakar Karthikeyan, and Jacob Reglend, "A 32 bit mac unit design using vedic multiplier and reversible logic gate," International Conference on Circuits, Power and Computing Technologies, 2015, pp. 1-6. IEEE, 2015. 9.       Saravanan, Subramanian. "Design and Implementation of efficient reversible arithmetic and Logic Unit," Circuits and Systems, 2016, No. 6, pp. 630. Ravi, Vijay Prakash, Madan, “Design and Implementation of Vedic Multipliers Using Reversible Logic Gates,” Journal of Electric and Electronic Systems, 2018. DOI: 10.4172/2332-0796.1000255.