DESIGN AND IMPLEMENTATION OF SATURATION-BASED IMAGE DEHAZING ALGORITHM

This work presents a hardware-efficient VLSI implementation of an image dehazing algorithm that integrates the Dark Channel Prior (DCP) with saturation-based transmission estimation for FPGA deployment. By employing a 5×5 minimum filter on a down sampled image, the proposed architecture achieves accurate atmospheric light estimation while reducing computational complexity and hardware resource utilization. Experimental results demonstrate that the design provides an effective balance between image restoration quality and hardware efficiency, making it well suited for real-time embedded vision applications.   MATLAB-based validation and Verilog HDL implementation on the Zynq-7000 FPGA demonstrate that the proposed architecture achieves improved image restoration performance in terms of PSNR and SSIM while reducing hardware resource utilization compared to existing VLSI dehazing designs. The optimized processing pipeline and compact 5×5 filter enhance both visual quality and computational efficiency. Furthermore, the FPGA implementation exhibits low power consumption and efficient logic utilization, making the proposed architecture well suited for real-time, low-power embedded vision applications.   In conclusion, the proposed work effectively bridges the gap between image restoration performance and hardware efficiency in FPGA-based dehazing systems. The integration of Dark Channel Prior (DCP) and saturation-based transmission estimation enables robust haze removal while preserving fine image details. Future work will focus on adaptive filter window selection, hardware-efficient image enhancement techniques, and high-level synthesis optimizations to further improve scalability and performance for real-time vision applications, including autonomous navigation, intelligent surveillance, and remote sensing

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