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Stream/Area:
-
Subject:
-
Paper ID:
IJSREM66541
Volume:
10 |
8 |
Aug 2026
Pages:
1-3
Publication Frequency:
Monthly (12 issues per year)
License:International Journal of Scientific Research in Engineering and Management follows the Creative Commons Attribution 4.0 (CC BY 4.0) License, allowing free use and distribution with proper attribution.
ECE
JNNCE, SHIMOGA
ECE
JNNCE, SHIMOGA
ECE
JNNCE, SHIMOGA
ECE
JNNCE, SHIMOGA
Edge detection is a fundamental operation in digital image processing essential for object boundary identification, feature extraction, and computer vision systems. Among conventional approaches, the Sobel edge detection algorithm is highly favored due to its algorithmic simplicity and effective edge enhancement capabilities. However, software-based execution on general-purpose central processing units (CPUs) exhibits critical bottlenecks in throughput, processing latency, and power consumption, rendering it inefficient for high-frame-rate, real-time applications. To address these operational constraints, this paper presents the design and implementation of a high-speed, fully pipelined Sobel Edge Detection Hardware Accelerator utilizing a standard Very Large Scale Integration (VLSI) digital design flow. The architecture relies on an optimized three-stage pipeline consisting of an arrayed line buffer, a 3\times3 sliding window generator, and a combinational gradient computation block utilizing the hardware-efficient Manhattan approximation. Described in synthesizable Verilog Register Transfer Level (RTL), the architecture is compiled and functionally verified using Cadence NCLaunch and SimVision waveform tools. Operating at a clock frequency of 100 MHz, the proposed hardware accelerator accomplishes a deterministic throughput of one pixel per clock cycle with a fixed pipeline latency of three clock cycles. The system provides an optimal infrastructure for deployment on high-speed embedded platforms like field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) targeted at automated systems, medical imaging, and autonomous vehicles.
KEYWORDS
This paper presented the design and functional verification of a fully pipelined Sobel Edge Detection Hardware Accelerator engineered through an industry-standard VLSI digital design flow. By combining parameterized shift-register arrays with a combinational Manhattan approximation computation block, the system achieves a deterministic throughput of one pixel per clock cycle at 100 MHz after an initial three-cycle latency penalty. Functional waveforms validated exact structural boundary identification by successfully clamping peak edge vectors to maximum intensity (8'hFF) and uniform regions to zero (8'h00).
1. S. Deepa and S. Bhavani, "FPGA Implementation of Sobel Edge Detection Algorithm," in Proceedings of IEEE International Conference on Computing, Communication and Networking Technologies (ICCCNT), Hefei, China, 2014, doi: 10.1109/ICCCNT.2014.6963128. 2. K. Huang, Y. Ye, and Y. Zhang, "Design and Implementation of Real Time Edge Detection Circuit Using Sobel Operator Based on FPGA," in Proceedings of IEEE International Conference on Industrial Electronics and Applications (ICIEA), Beijing, China, 2011, doi: 10.1109/ICIEA.2011.5975760. 3. M. Suresh, T. Bhavani, and N. Krishnamurthy, "High Speed Sobel Edge Detection Using Pipelined Architecture in VLSI," in Proceedings of IEEE International Conference on Signal Processing, Communication and Networking (ICSCN), Chennai, India, 2015, doi: 10.1109/ICSCN.2015.7219907. 4. R. Ramesh and S. Malarkkan, "Low Power and High Speed VLSI Architecture for Sobel Edge Detection Using Cadence Tools," in Proceedings of IEEE International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, India, 2016, doi: 10.1109/ICCSP.2016.7754209. 5. P. Harinarayana and N. V. Subba Reddy, "An Efficient Hardware Architecture for Sobel Edge Detection in Real Time Image Processing Applications," IEEE Access, vol. 7, pp. 87488–87497, 2019, doi: 10.1109/ACCESS.2019.2925919.
Publication Date
8/5/2026
Peer Review Type
Double-Blind Peer Review
Review Rounds: 2
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Conflict of Interest
The authors declare no conflict of interest related to this research work.
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