Design and Implementation of UART using Verilog HDL and FPGA

Implementation of UART using Verilog HDL and FPGA

Ms. Aruna Dore1, K.H.N.M.Ramakrishna2, L.premanandareddy3,

 Vageesh A4, pritham ashok rudrapur5

 1Assistant Professor, Electronics and Communication Engineering, Presidency University

2Student, Electronics and Communication Engineering, Presidency University

3Student, Electronics and Communication Engineering, Presidency University

4Student, Electronics and Communication Engineering, Presidency University

4Student, Electronics and Communication Engineering, Presidency University

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Abstract -

This study presents a hardware-based implementation of Universal Asynchronous Receiver Transmitter (UART) communication on the Nexys A7-100T Field Programmable Gate Array (FPGA) platform using Verilog HDL and Vivado Design Suite. UART serves as a fundamental serial communication protocol, widely adopted due to its simplicity and effectiveness. The work details the design methodology, including clock division, baud rate generation, and serial data transmission, while demonstrating successful communication between FPGA and PC. Experimental results confirm reliable and low-power serial data exchange, making this implementation ideal for embedded and communication systems.

Keywords

UART, FPGA, Serial Communication, Verilog HDL, Nexys A7-100T, Vivado, VLSI, Clock Gating