Design and Optimization of an Ultra-Low-Power Successive Approximation ADC for IoT Applications

Design and Optimization of an Ultra-Low-Power Successive Approximation ADC for IoT Applications

Vignesh H*1, Dr Vasudeva G2

1Under Graduate Student, Department of Electronics and Communication, Dayananda Sagar Academy of Technology and Management, Bangalore, Karnataka, India

2Professor, Department of Electronics and Communication, Dayananda Sagar Academy of Technology and Management, Bangalore, Karnataka, India

*Corresponding Author:vigneshhari872002@gmail.com

Abstract
This paper presents the design and optimization of an ultra-low-power successive approximation analog-to-digital converter (ADC) tailored for Internet of Things (IoT) applications. The proposed ADC architecture leverages low-power design techniques to achieve high resolution and sampling rates while minimizing power consumption. A novel combination of capacitor splitting and dynamic biasing techniques is employed to reduce energy consumption during the conversion process. Moreover, the ADC features a digital background calibration scheme to compensate for process variations and non-idealities, ensuring accurate conversion performance over varying operating conditions. The ADC is implemented in a standard CMOS process and achieves a resolution of 10 bits with a sampling rate of 100 kS/s while consuming only 50 µW of power from a 1.2 V supply. Simulation results demonstrate the effectiveness of the proposed design in achieving high energy efficiency and robust performance suitable for IoT sensor nodes and other battery-operated devices.