Design and Simulation of Clock Divider using VHDL

Design and Simulation of Clock Divider using VHDL

Archana Patil1, Dr. Mrs. S.W. Varade2, Sharda Mungale3

1Student, Department of Electronics & Telecommunication Engineering, Priyadarshini College of Engineering, Nagpur, India

2Professor, Department of Electronics & Telecommunication Engineering, Priyadarshini College of Engineering, Nagpur, India

3Assistant Professor, Department of Internet of Thing (IOT) Engineering, Priyadarshini College of Engineering, Nagpur, India

Abstract

This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers.

Keywords:- clock divider, D flipflop, FPGA